The invention pertains to methods of forming insulative materials against conductive structures, and in particular aspects pertains to methods of forming transistor structures. Also, the invention pertains to transistor structures.
A frequently used procedure of semiconductor fabrication is formation of a so-called xe2x80x9cself-aligned contactxe2x80x9d (SAC) opening. An exemplary use of a SAC opening is to expose a node between a pair of wordlines, and can be conducted as follows. First, a pair of adjacent wordlines are formed over a substrate, and then insulative sidewall spacers are formed along conductive portions of the lines. The wordlines typically comprise conductive portions capped by insulative material. Suitable insulative material for capping the wordlines is silicon nitride. A thick insulative layer (typically borophosphosilicate glass (BPSG)) is formed over the wordlines and insulative sidewall spacers. The insulative sidewall spacers are formed of a material different than the thick insulative layer, with a suitable material being silicon nitride.
An opening is etched through the thick insulative layer and to an electrical node between the wordlines. If the thick insulative layer comprises BPSG and the sidewall spacers comprise silicon nitride, the etch utilizes conditions which are selective for the BPSG relative to the silicon nitride. The insulative spacers are exposed during formation of the opening, but are etched more slowly than the BPSG, and preferably are not entirely removed by the etch of the BPSG. The opening is intended to be formed to have a periphery xe2x80x9calignedxe2x80x9d with the spacers, and the formation of the opening is referred to as a xe2x80x9cself-aligned a contactxe2x80x9d etch.
It is desired that the spacers not be entirely removed during formation of the opening so that the spacers can protect the conductive material of the wordlines from being exposed when the opening is formed. If the conductive material of the wordlines becomes exposed in the openings, device failure will likely result. A problem with current semiconductor fabrication processes is that silicon nitride insulative spacers are occasionally over-etched during formation of contact openings in BPSG, leading to exposure of wordline conductive material, and to device failure.
A possible method for overcoming the above-discussed problem is described in U.S. Pat. No. 5,700,349, which suggests utilizing SixOyNz or AlxOy based materials to protect conductive portions of a wordline during a SAC method. The utilization of SixOyNz and AlxOy as protective materials relative to the conductive material of a wordline during a SAC method shows promise, in that SixOyNz and AlxOy appear to be more resistant to SAC etch conditions than is a silicon nitride protective material. However, the materials of U.S. Pat. No. 5,700,349 have problems associated with their use, and it would be desirable to overcome such problems.
In one aspect, the invention encompasses a method of forming an insulative material along a conductive structure. A conductive structure is provided over a substrate, and an electrically insulative material is formed along at least a portion of the conductive structure. The electrically insulative material comprises at least one of SixOyNz and AlpOq, wherein p, q, x, y and z are greater than 0 and less than 10. A dopant barrier layer is formed over the electrically insulative material. BPSG is formed over the dopant barrier layer, and the dopant barrier layer prevents dopant migration from the BPSG to the electrically insulative material.
In another aspect, the invention encompasses methods of forming transistor structures.
In yet another aspect, the invention encompasses a transistor structure which includes a transistor gate formed over a semiconductive substrate. The transistor gate has a sidewall which comprises electrically conductive material. Source/drain regions are within the substrate and proximate the transistor gate. An electrically insulative material is along the electrically conductive material of the sidewall of the transistor gate. The electrically insulative material comprises at least one of SixOyNz and AlpOq, wherein p, q, x, y and z are greater than 0 and less than 10. A layer consisting of silicon dioxide is over the transistor gate, electrically insulative material and substrate. A layer of BPSG is over the layer consisting of silicon dioxide.